Reflective mask, manufacturing method for reflective mask, and manufacturing method for semiconductor device

ABSTRACT

A reflective mask comprising: a reflective layer that is arranged on a surface on a side on which EUV light is irradiated and reflects the EUV light; a buffer layer containing Cr that is arranged on a side of the reflective layer on which the EUV light is irradiated and covers an entire surface of the reflective layer; and a non-reflective layer that is arranged on a side of the buffer layer on which the EUV light is irradiated and in which an absorber that absorbs the irradiated EUV light is arranged in a position corresponding to a mask pattern to be reduced and transferred onto a wafer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2008-193131, filed on Jul. 28,2008; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a reflective mask, a manufacturingmethod for the reflective mask, and a manufacturing method for asemiconductor device.

2. Description of the Related Art

Extreme ultraviolet (EUV) lithography is an exposure method in whichlight (an X ray) having extremely short wavelength near 13.5 nanometersis used. The EUV lithography is prospective as a method of forming afiner pattern on a wafer than that formed by light exposure in the past(having wavelength of 193 manometers (ArF) or 248 nanometers (KrF).

The pattern formed on the wafer by the EUV lithography is, for example,a pattern smaller than 50 nanometers. Therefore, a technical levelrequired for defect inspection and defect correction for a mask forforming a pattern to be transferred onto the wafer is high. For example,to form a pattern having width of 32 nanometers on the wafer using amask of tetraploid, it is necessary to form a pattern having width of128 nanometers on the mask. To keep fluctuation in a pattern dimensionon the wafer within 5%, it is necessary to keep dimension fluctuation ofa mask pattern within 6.4 nanometers. Therefore, it is necessary toperform inspection of the mask pattern at accuracy of a dimension equalto or smaller than 6.4 nanometers. When a pattern finer than 32nanometers is formed on the wafer, it is necessary to inspect the maskpattern in specifications stricter than 6.4 nanometers.

In the past, a reflective mask used for EUV exposure and the like ismanufactured by arranging an EUV light absorber (a Ta compound, etc.) ona mask and etching the absorber according to a pattern to be exposed. Insuch a reflective mask, a buffer layer formed of Cr, a Cr compound suchas CrN, or the like is arranged below an absorber layer as an etchingstop layer (see, for example, Japanese Patent Application Laid-Open No.2006-13494). The buffer layer is necessary for obtaining signal contrastwith the absorber not only during the etching of the absorber but alsoduring inspection of a mask pattern by an electron microscope. Duringmask pattern formation, the buffer layer is present over the entire maskbetween the absorber and a Mo/Si multilayer film for reflecting EUVlight. Such a buffer layer causes deterioration in the intensity ofreflected light. Therefore, after formation of an absorber pattern, asection without the absorber is etched and removed to expose the Mo/Simultilayer.

However, in the technology in the past, the inspection of the maskpattern is performed before the etching and removal of the buffer layer,i.e., the etching and removal of the buffer layer is performed after theinspection. Therefore, a defect that occurs in this etching process isnot inspected. Examples of the defect that occurs in the etching processfor the buffer layer include a partial (local) etching removal residueof a buffer layer material and a pattern dimension change due toredeposit of the removed buffer layer material on the absorber pattern.Therefore, a pattern is formed on the wafer by the mask in which thedefect occurs. As a result, a pattern cannot be formed on the wafer in adesired dimension.

BRIEF SUMMARY OF THE INVENTION

A reflective mask according to an embodiment of the present inventioncomprises: a reflective layer that is arranged on a surface on a side onwhich EUV light is irradiated and reflects the EUV light;

a buffer layer containing Cr that is arranged on a side of thereflective layer on which the EUV light is irradiated and covers anentire surface of the reflective layer; and

a non-reflective layer that is arranged on a side of the buffer layer onwhich the EUV light is irradiated and in which an absorber that absorbsthe irradiated EUV light is arranged in a position corresponding to amask pattern to be reduced and transferred onto a wafer.

A manufacturing method for a reflective mask according to an embodimentof the present invention comprises: forming a reflective layer thatreflects EUV light on a surface on a side on which the EUV light isirradiated;

forming a buffer layer containing Cr that covers an entire surface ofthe reflective layer on the side of the reflective layer on which theEUV light is irradiated; and forming, as a non-reflective layer, anabsorber that absorbs the irradiated EUV light on the side of the bufferlayer on which the EUV light is irradiated and in a positioncorresponding to a mask pattern to be reduced and transferred onto awafer.

A manufacturing method for a semiconductor device according to anembodiment of the present invention comprises: forming a reflectivelayer that reflects EUV light on a surface on a side on which the EUVlight is irradiated;

forming a buffer layer containing Cr that covers an entire surface ofthe reflective layer on the side of the reflective layer on which theEUV light is irradiated;

forming, as a non-reflective layer, an absorber that absorbs theirradiated EUV light on the side of the buffer layer on which the EUVlight is irradiated and in a position corresponding to a mask pattern tobe reduced and transferred onto a wafer; and

manufacturing a semiconductor device using a reflective mask includingthe reflective layer, the buffer layer, and the non-reflective layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a configuration of a mask according to a firstembodiment of the present invention;

FIG. 2 is a diagram for explaining a relation between the thickness of abuffer layer and exposure conditions;

FIG. 3 is a diagram of a configuration of a mask in the past;

FIG. 4 is a diagram of another configuration example of the maskaccording to the first embodiment;

FIG. 5 is a diagram of a configuration of a mask according to a secondembodiment of the present invention; and

FIG. 6 is a diagram of another configuration example of the maskaccording to the second embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Exemplary embodiments of the present invention are explained in detailbelow with reference to the accompanying drawings. The present inventionis not limited by the embodiments.

FIG. 1 is a diagram of a configuration of a mask according to a firstembodiment of the present invention. In FIG. 1, a sectional view of amask 10 is shown. The mask 10 is a reflective mask used for EUV exposureand includes an absorber (a non-reflective layer) 2, a buffer layer 3, acapping layer 4, and a reflective film (a reflective layer) 5. In themask 10 shown in FIG. 1, the absorber 2 is formed on the upper surfaceside of the reflective film 5. However, when the mask 10 is mounted onan exposure apparatus, the mask 10 can be reversed and mounted.Specifically, the mask 10 can be mounted on the exposure apparatus withthe absorber 2 set on the upper surface side or can be mounted on theexposure apparatus with the absorber 2 set on the lower surface side.

In the mask 10, the reflective film 5 is arranged on a glass substrate(not shown in the figure). The capping layer 4 is arranged on the upperside of the reflective film 5 and covers the entire surface of thereflective film 5. The buffer layer 3 is arranged on the upper side ofthe capping layer 4 and covers the entire surface of the capping layer4. The patterned absorber 2 is arranged on the upper side of the bufferlayer 3 and covers a part of the buffer layer 3. When the EUV exposureis performed by using the mask 10, EUV light is made obliquely incidentfrom the absorber 2 side (a front surface side).

The reflective film 5 includes a material that reflects the EUV light.The reflective film 5 is, for example, an Mo/Si multilayer film. TheMo/Si multilayer film is a multilayer film formed by alternatelystacking 4 nanometers of molybdenum (Mo) layers and silicon (Si) layerswith thickness of, for example, 4 nanometers. A layer at the top layer(a layer directly joined with the capping layer 4) of the Mo/Simultilayer film can be a molybdenum layer or a silicon layer.

The capping layer 4 is a film for capping the reflective film 5 and is,for example, a silicon film. The capping layer 4 prevents oxidation ofthe film at the top layer of the multilayer film by covering the entiresurface of the reflective film 5. The capping layer 4 has thickness of,for example, 10 nanometers.

The buffer layer 3 is an etch stop layer used when etching and defectcorrection for the absorber 2 are performed and is formed of, forexample, Cr or a Cr compound. Therefore, the buffer layer 3 is formed ofa material having a large selection ratio between the buffer layer 3 andthe absorber 2 during etching. The buffer layer 3 has thickness of, forexample, 3 nanometers. The absorber 2 includes a material that absorbsEUV light. The absorber 2 is formed of, for example, a Ta compound andhas thickness of, for example, 70 nanometers.

To manufacture the mask 10, the absorber 2 is etched from a mask blankand patterned. The mask blank is a substrate including the reflectivefilm 5, the capping layer 4, the buffer layer 3, and the absorber 2 notpatterned. A resist material for absorber layer processing may beapplied to a layer of the absorber 2. Therefore, the mask blank is asubstrate in which the absorber 2 before patterning covers the entiresurface of the buffer layer 3. Thereafter, in this embodiment, themanufacturing of the mask 10 is completed without etching the bufferlayer 3. Therefore, in the mask 10 according to this embodiment, thebuffer layer 3 is present in both a section where the absorber 2 is notpresent (a section where the absorber 2 is etched) and a section wherethe absorber 2 is present (the buffer layer 3 is present on the entiresurface of the capping layer 4).

EUV light irradiated on the vicinity of the absorber 2 in the EUV lightirradiated on the mask 10 is absorbed by the absorber 2. EUV lightirradiated on a position (the buffer layer 3) other than the absorber 2is reflected on the buffer layer 3 and the reflective film 5 of a lowerlayer of the buffer layer 3. Consequently, only the EUV light reflectedon the buffer layer 3 and the reflective film 5 of the lower layer ofthe buffer layer 3 is sent to a wafer (not shown in the figure). Apattern corresponding to the pattern of the absorber 2 is reduced andtransferred onto the wafer. The capping layer 4 and the reflective film5 are separately formed. However, the capping layer 4 and the reflectivelayer 5 can be integrally formed.

An expose amount (a dose) and contrast necessary for forming a patternon the wafer changes according to the thickness of the buffer layer 3.Therefore, in this embodiment, the buffer layer 3 having appropriatethickness for obtaining a predetermined dose is formed on the mask 10while securing predetermined contrast.

A relation between the contrast of EUV light irradiated on the wafer andthe thickness of the buffer layer 3 and a relation between a dosenecessary for forming a pattern on the wafer and the thickness of thebuffer layer 3 are explained. In the following explanation, a transferpattern on the wafer is lines and spaces arranged at intervals of 32nanometers (1:1 equal interval array of 32 nanometers in width).

FIG. 2 is a diagram for explaining a relation between the thickness of abuffer layer and exposure conditions. In FIG. 2, a calculation result ofcontrast and a calculation result of an optimum dose are shown. Thecontrast is the contrast of EUV light irradiated on the wafer via themask 10. The contrast is calculated by using, for example, a maximum(max) and a minimum (min) of light intensity of the EUV light irradiatedon the wafer. Contrast C is a value calculated by a formulaC=(max−min)/(max+min). The optimum dose is an exposure amount necessaryfor forming a pattern on the wafer and is standardized.

In FIG. 2, a calculation result obtained when EUV exposure is performedby the mask in the past and a calculation result obtained when EUVexposure is performed by the mask 10 according to this embodiment areshown. The thickness of the buffer layer in the past is the thickness ofthe buffer layer 3 present below the absorber 2. Contract C1 is contrastobtained when EUV exposure is performed by the mask in the past.Contrast C2 is contrast obtained when EUV exposure is performed by themask 10 according to this embodiment. A dose D1 is an optimum doseobtained when EUV exposure is performed by the mask in the past. A doseD2 is an optimum dose obtained when EUV exposure is performed by themask 10 according to this embodiment.

FIG. 3 is a diagram of a configuration of the mask in the past. In FIG.3, a sectional view of a mask 60 in the past is shown. In the mask 6 inthe past, a part (a section except a section below the absorber 2) of abuffer layer 63 is etched from the mask 60 and the buffer layer 63except the section below the absorber 2 is removed. Therefore, thecapping layer 4 is exposed in a section except a position where theabsorber 2 is formed. Specifically, in the mask 60, the reflective film5 is arranged on a glass substrate. The capping layer 4 is arranged onthe upper side of the reflective film 5 and covers the entire surface ofthe reflective film 5. The patterned buffer layer 63 is arranged on theupper side of the capping layer 4 and covers a part of the capping layer4. The patterned absorber 2 is arranged on the upper side of the bufferlayer 63 and covers a part of the buffer layer 63. In the mask 60, thebuffer layer 63 and the absorber 2 are patterned in the same shape.

It is seen that, when the thickness of the buffer layers 3 and 63 isgradually reduced from 15 nanometers, the contrasts C1 and C2 change.

In the past, the thickness of a buffer layer is 10 nanometers to 15nanometers. The contrast C1 is larger than the contrast C2 in thisthickness. Depending on a thickness condition of the buffer layer 3, thecontrast C2 obtained when the buffer layer 3 is left on the reflectingsection is larger than the contrast C1. It is seen that, for example,when the thickness of the buffer layer 3 is 5 nanometers to 6nanometers, sufficient contrast is obtained even if the buffer layer 3is not etched and removed.

When the intensity of reflected light decreases, it is necessary toextend exposure time for obtaining an exposure amount of EUV lightnecessary for forming a desired pattern on a wafer. Therefore,throughput of exposure is deteriorated. Therefore, in this embodiment,the buffer layer 3 having thickness with which a pattern can be formedon the wafer with exposure time for not deteriorating the throughput ofexposure is used.

In FIG. 2, the doses D1 and D2 are calculated with reference to a dosenecessary when a buffer layer is etched and removed and the thickness ofthe buffer layer is 15 nanometers. As indicated by the dose D1, when thebuffer layer 63 is etched and removed, a substantially fixed dose isnecessary irrespective of the thickness of the buffer layer 63. On theother hand, as indicated by the dose D2, when the buffer layer 3 is notetched and removed and is left in the reflecting section, the necessarydose decreases as the thickness of the buffer layer 3 decreases.

In the case of the dose D2, when the thickness of the buffer layer 3decreases to be equal to or smaller than 3 nanometers, a pattern can beformed on the wafer with a dose substantially equal to a dose obtainedwhen the buffer layer 63 is etched and removed. When a slight increasein the dose is allowed, even when the buffer layer 3 has thickness of 4nanometers to 5 nanometers, it is possible to omit the etching andremoval of the buffer layer 3.

Even in a mask structure in which the buffer layer 3 is not etched andremoved (a mask structure in which the buffer layer 3 is left in thereflecting section) as explained above, it is seen that there is thethickness of the buffer layer 3 with which sufficient contrast can beobtained and EUV exposure can be performed with a dose in an allowablerange.

In this embodiment, for example, the thickness of the buffer layer 3 isoptimized by applying, for example, thickness equal to or smaller than 3nanometers as the thickness of the buffer layer 3. By determining theoptimum thickness of the buffer layer 3 in this way, it is possible toomit an etching and removing process for the buffer layer 3 in a processfor manufacturing a reflective mask for EUV. A semiconductor device ismanufactured by using, for EUV exposure processing, the mask 10manufactured as explained above.

In the explanation of this embodiment, the lines and spaces arranged atthe intervals of 32 nanometers are subjected to EUV exposure. A shapeand the size of a pattern to be subjected to EUV exposure can be anyshape and size. When a plurality of kinds of patterns are included inthe pattern to be subjected to EUV exposure, thickness optimized for asmallest pattern shape is applied.

In the explanation of the embodiment, the mask 10 includes the cappinglayer 4. However, a mask does not have to include the capping layer 4.FIG. 4 is a diagram of another configuration example of the maskaccording to the first embodiment. In FIG. 4, a sectional view of a mask11 is shown. The mask 11 includes the absorber 2, the buffer layer 3,and the reflective film 5.

In the mask 11, the reflective film 5 is arranged on a glass substrate.The buffer layer 3 is arranged on the upper side of the reflective film5 and covers the entire surface of the reflective film 5. The patternedabsorber 2 is arranged on the upper side of the buffer layer 3 andcovers a part of the buffer layer 3.

When the mask 11 is configured such as explained above, the buffer layer3 functions as a capping layer. As explained above, because the mask 11does not include the capping layer 4, the mask 11 is simpler than themask 10. Further, the reflecting section of the mask 11 can reflect EUVlight at reflectance larger than that of the reflecting section of themask 10.

In this embodiment, because the buffer layer 3 and the capping layer 4are not etched, an etching selection ratio between the buffer layer 3and the capping layer 4 can be small. Therefore, the capping layer 4 canbe formed of a material different from silicon.

Even when foreign particles or the like adhere to the reflecting sectionof the mask 10, because the buffer layer 3 covers an upper part of thereflecting section, damage to the capping layer 4 and the reflectivefilm 5 in foreign particle removal (defect correction for the absorber2) by a focused ion beam (FIB), an electron beam, or an atomic forcemicroscope (AFM) can be prevented. Consequently, a phase defect of themask 10 can be reduced. Because etching of the buffer layer 3 is notperformed, occurrence of a defect due to a removal residue of the bufferlayer 3 can be prevented. Further, foreign particles can be preventedfrom depositing on the absorber 2. Because manufacturing processes forthe mask 10 can be reduced in this way, processes that could causedeterioration in dimension controllability decrease. Therefore, it ispossible to form a pattern on a wafer in a dimension as designed.Consequently, yield in manufacturing a semiconductor device using themask 10 is improved. Further, because it is possible to form a finepattern with occurrence of a defect prevented, it is possible tomanufacture a semiconductor device having high performance.

Because the etching and removal process for the buffer layer 3 can beomitted, it is possible to manufacture the mask 10 at low cost andmanufacture the mask 10 in a short period. In other words, maskmanufacturing turn around time (TAT) can be reduced and manufacturingcost can be reduced through a reduction in the number of steps of themask manufacturing process. As a result, the mask 10 and a semiconductordevice manufactured by using the mask 10 can be put on the market atearlier timing and an opportunity loss can be reduced.

As explained above, according to the first embodiment, the buffer layer3 of the mask 10 or 11 is arranged on the upper side of the reflectivefilm 5 without being etched. Therefore, pattern dimensioncontrollability in forming a pattern on a wafer with the mask 10 or 11is improved. In other words, a dimension of a pattern formed on thewafer can be accurately controlled.

In a second embodiment of the present invention, the buffer layer 3 isetched by predetermined thickness to form the buffer layer 3 havingdesired thickness in a mask.

FIG. 5 is a diagram of a configuration of a mask according to the secondembodiment. In FIG. 5, a sectional view of a mask 12 is shown.Components shown in FIG. 5 that attain functions same as those of themask 10 according to the first embodiment shown in FIG. 1 are denoted bythe same reference numerals and redundant explanation of the componentsis omitted.

In the mask 12, the reflective film 5 is arranged on a glass substrate(not shown). The capping layer 4 is arranged on the upper side of thereflective film 5 and covers the entire surface of the reflective film5. The buffer layer 3 is arranged on the upper side of the capping layer4 and covers the entire surface of the capping layer 4. The buffer layer3 in this embodiment is etched from a mask blank by predeterminedthickness. Therefore, the thickness of the buffer layer 3 is differentin a reflecting section of the mask 12 and a non-reflecting section ofthe mask 12 (a lower part of the absorber 2). The patterned absorber 2is arranged as a non-reflecting section on the upper side of the bufferlayer 3 and covers a part of the buffer layer 3.

To manufacture the mask 12, the absorber 2 is etched from the mask blankand patterned. Further, in this embodiment, the buffer layer 3 is etchedby predetermined thickness to have predetermined final thickness (e.g.,3 nanometers) in a place where the absorber 2 is not present.Consequently, the buffer layer 3 having the predetermined thickness isformed in the mask 12 to complete the manufacturing of the mask 12.Therefore, in the mask 12 according to this embodiment, the buffer layer3 is present in both a section where the absorber 12 is not present anda section where the absorber 2 is present.

The thickness of the buffer layer 3 in the reflecting section of themask 12 is set to thickness (e.g., equal to or smaller than 3nanometers) calculated by a calculation method same as that in the firstembodiment explained with reference to FIG. 2. This makes it possible toobtain the mask 12 having merits same as those of the mask 10 accordingto the first embodiment.

In the explanation of this embodiment, the mask 12 includes the cappinglayer 4. However, a mask does not have to include the capping layer 4.FIG. 6 is a diagram of another configuration example of the maskaccording to the second embodiment. In FIG. 6, a sectional view of themask 13 is shown. The mask 13 includes the absorber 2, the buffer layer3, and the reflective film 5.

In the mask 13, the reflective film 5 is arranged on a glass substrate.The buffer layer 3 is arranged on the upper side of the reflective film5 and covers the entire surface of the reflective film 5. The patternedabsorber 2 is arranged on the upper side of the buffer layer 3 andcovers a part of the buffer layer 3.

When the mask 13 is configured such as explained above, the buffer layer3 functions as a capping layer. As explained above, because the mask 13does not include the capping layer 4, the mask 13 is simpler than themask 12. Further, the reflecting section of the mask 13 can reflect EUVlight at reflectance larger than that of the reflecting section of themask 12.

As explained above, according to the second embodiment, the buffer layer3 of the mask 12 or 13 is etched to have predetermined thickness tooptimize the thickness of the buffer layer 3. Therefore, patterndimension controllability in forming a pattern on a wafer with the mask12 or 13 is improved.

Because the buffer layer 3 is etched, it is possible to easily form thebuffer layer 3 having desired thickness corresponding to exposureconditions. Further, because the thickness of the buffer layer 3 isoptimized, it is possible to form a pattern on a wafer withoutincreasing an optimum dose.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1.-20. (canceled)
 21. A manufacturing method for a semiconductor device,comprising: manufacturing a semiconductor device using a reflective maskthat reflects EUV light to a wafer, the reflective mask including areflective layer that reflects the EUV light, a buffer layer containingCr that is arranged on the reflective layer and covers an entire surfaceof the reflective layer, and an absorber, arranged on the reflectivelayer, to absorb the EUV light, the absorber being used as a maskpattern to be reduced and transferred onto a wafer, wherein a thicknessof the buffer layer is selected such that a difference between a firstcontrast and a second contrast falls in an allowable range, the firstcontrast being a contrast between the EUV light reflected on thereflective layer and with which the wafer is irradiated, and the EUVlight reflected on the absorber and with which the wafer is irradiatedwhen the buffer layer is arranged only below the absorber, and thesecond contrast being a contrast between the EUV light reflected on thereflective layer and with which the wafer is irradiated, and the EUVlight reflected on the absorber and with which the wafer is irradiatedwhen the buffer layer is arranged on the entire surface of thereflective layer.
 22. The manufacturing method for a semiconductordevice, according to claim 21, wherein a thickness of the buffer layerlocated below the absorber is larger than a thickness in a positionwhere the absorber is not formed on the buffer layer.
 23. Themanufacturing method for a semiconductor device, according to claim 21,wherein the reflective mask further includes a capping layer that coversthe entire surface of the reflective layer between the reflective layerand the buffer layer, wherein a first exposure amount of the EUV lightis an exposure amount necessary for forming a pattern on the wafer and asecond exposure amount of the EUV light is an exposure amount necessaryfor forming a pattern on the wafer when the buffer layer is present onlybelow the absorber, the thickness of the buffer layer is selected suchthat a difference between the first exposure amount and the secondexposure amount falls in an allowable range.
 24. The manufacturingmethod for a semiconductor device, according to claim 21, wherein thereflective mask further includes a capping layer that covers the entiresurface of the reflective layer between the reflective layer and thebuffer layer, wherein the buffer layer covers the entire surface of thereflective layer by covering an entire surface of the capping layer. 25.The manufacturing method for a semiconductor device, according to claim21, wherein the reflective layer is an Mo/Si multilayer film formed byalternately stacking molybdenum and silicon, and a top layer of thereflective layer and the buffer layer are directly set in contact witheach other.
 26. The manufacturing method for a semiconductor device,according to claim 21, wherein the buffer layer is formed of Cr or a Crcompound.
 27. The manufacturing method for a semiconductor device,according to claim 21, wherein the thickness of the buffer layer is 5nanometers to 6 nanometers.
 28. The manufacturing method for asemiconductor device, according to claim 21, wherein the thickness ofthe buffer layer is equal to or smaller than 3 nanometers.
 29. Themanufacturing method for a semiconductor device, according to claim 21,wherein the thickness of the buffer layer is 4 nanometers to 5nanometers.
 30. The manufacturing method for a semiconductor device,according to claim 23, wherein a material of the capping layer is amaterial containing silicon.